View ADM1175-2ARMZ-R7_2476511.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hot swap controller and digital power monitor with convert pin adm1175 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features allows safe board insertion and removal from a live backplane controls supply voltages from 3.15 v to 16.5 v precision current sense amplifier precision voltage input 12-bit adc for current and voltage readback charge pumped gate drive for external n-channel fet adjustable analog current limit with circuit breaker 3% accurate hot swap current limit level fast response limits peak fault current automatic retry or latch-off on current fault programmable hot swap timing via timer pin active-high and active-low on/onb pin options convert start pin (conv) i 2 c? fast mode-compliant interface (400 khz maximum) 10-lead msop applications power monitoring/power budgeting central office equipment telecommunication and data communication equipment pcs/servers general description the adm1175 is an integrated hot swap controller and current sense amplifier that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (adc), communicated through an i 2 c interface. an internal current sense amplifier senses voltage across the sense resistor in the power path via the vcc pin and the sense pin. the adm1175 limits the current through this resistor by control- ling the gate voltage of an external n-channel fet in the power path, via the gate pin. the sense voltage (and, therefore, the inrush current) is kept below a preset maximum. the adm1175 protects the external fet by limiting the time that it spends with maximum current running through it. this current limit period is set by the choice of capacitor attached to the timer pin. additionally, the device provides protection from overcurrent events that may occur once the hot swap event is complete. in the case of a short-circuit event, the current in the sense resistor exceeds an overcurrent trip threshold, and the fet is switched off immediately by pulling down the gate pin. functional block diagram v i 0 1 adm1175-1 sense on vcc conv 1.3v mux i 2 c 12-bit adc fet drive controller gnd current sense amplifier uv comparator a sda scl adr gate timer 05647-001 figure 1. r sense n-channel fet p = vi controller adm1175-1 sense vcc sda scl sda scl gnd gate conv conv adr timer 3.15v to 16.5 v on 05647-002 figure 2. applications diagram a 12-bit adc can measure the current seen in the sense resistor, as well as the supply voltage on the vcc pin. an industry-standard i 2 c interface allows a controller to read current and voltage data from the adc. measurements can be initiated by an i 2 c command or via the convert (conv) pin. the conv pin is especially useful for synchronizing reads on multiple adm1175 devices. alternatively, the adc can run continuously, and the user can read the latest conversion data whenever it is required. up to four unique i 2 c addresses can be created, depending on the way the adr pin is connected. the adm1175 is packaged in a 10-lead msop.
adm1175 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 overview of the hot swap function............................................ 13 undervoltage lockout ............................................................... 13 on/onb function..................................................................... 13 timer function ........................................................................ 13 gate and timer functions during a hot swap ................ 14 calculating current limits and fault current limit time .. 14 initial timing cycle ................................................................... 14 hot swap retry cycle on the adm1175-1 and the adm1175-3 ................................................................................ 15 voltage and current readback ..................................................... 16 serial bus interface..................................................................... 16 identifying the adm1175 on the i 2 c bus............................... 16 general i 2 c timing.................................................................... 16 write and read operations ...................................................... 18 quick command........................................................................ 18 write command byte ................................................................ 18 write extended byte .................................................................. 19 read voltage and/or current data bytes ................................ 20 applications waveforms................................................................ 22 kelvin sense resistor connection ........................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 9/06revision 0: initial version
adm1175 rev. 0 | page 3 of 24 specifications v cc = 3.15 v to 16.5 v; t a = ?40c to +85c; typical values at t a = 25c, unless otherwise noted. table 1. parameter min typ max unit conditions vcc pin operating voltage range, v vcc 3.15 16.5 v supply current, i cc 1.7 2.5 ma undervoltage lockout, v uvlo 2.8 v v cc rising undervoltage lockout hysteresis, v uvlohyst 80 mv on/onb pin input current, i inon ?100 +100 na on/onb < 1.5 v ?2 +2 a rising threshold, v onth 1.26 1.3 1.34 v on/onb rising trip threshold hysteresis, v onhyst 35 50 65 mv glitch filter time 3 s conv pin input current, i inconv ?1 +1 a v conv(max) = 3.6 v trip threshold low, v convl 1.2 v trip threshold high, v convh 1.4 v sense pin input leakage, i sense ?1 +1 a v sense = v vcc overcurrent fault timing threshold, v octim 92 mv v octrim = (v vcc ? v sense ), fault timing starts on the timer pin overcurrent limit threshold, v lim 97 100 103 mv v lim = (v vcc ? v sense ), closed-loop regulation to a current limit fast overcurrent trip threshold, v ocfast 115 mv v ocfast = (v vcc ? v sense ), gate pull-down current turned on gate pin drive voltage, v gate 3 6 9 v v gate ? v vcc , v vcc = 3.15 v 9 11 13 v v gate ? v vcc , v vcc = 5 v 7 10 13 v v gate ? v vcc , v vcc = 16.5 v pull-up current 8 12.5 17 a v gate = 0 v pull-down current 1.5 ma v gate = 3 v, v vcc = 3.15 v 5 ma v gate = 3 v, v vcc = 5 v 7 ma v gate = 3 v, v vcc = 16.5 v timer pin pull-up current (power on reset), i timeruppor ?3.5 ?5 ?6.5 a initial cycle, v timer = 1 v pull-up current (fault mode), i timerupfault ?40 ?60 ?80 a during current fault, v timer = 1 v pull-down current (retry mode), i timerdnretry 2 3 a after current fault and during a cool-down period on a retry device, v timer = 1 v pull-down current, i timerdn 100 a normal operation, v timer = 1 v trip threshold high, v timerh 1.26 1.3 1.34 v timer rising trip threshold low, v timerl 0.175 0.2 0.225 v timer falling adr pin set address to 00, v adrlowv 0 0.8 v low state set address to 01, r adrlowz 135 150 165 k resistor to ground state, load pin with specified resistance for 01 decode set address to 10, i adrhighz ?1 +1 a open state, maximum load allowed on adr pin for 10 decode set address to 11, v adrhighv 2 5.5 v high state input current for 11 decode, i adrlow 3 10 a v adr = 2.0 v to 5.5 v input current for 00 decode, i adrhigh ?40 ?22 a v adr = 0 v to 0.8 v
adm1175 rev. 0 | page 4 of 24 parameter min typ max unit conditions monitoring accuracy 1 current sense absolute accuracy ?1.45 +1.45 % v sense = 75 mv 0c to +70c ?1.8 +1.8 % v sense = 50 mv 0c to +70c ?2.8 +2.8 % v sense = 25 mv 0c to +70c ?5.7 +5.7 % v sense = 12.5 mv 0c to +70c ?1.5 +1.5 % v sense = 75 mv 0c to +85c ?1.8 +1.8 % v sense = 50 mv 0c to +85c ?2.95 +2.95 % v sense = 25 mv 0c to +85c ?6.1 +6.1 % v sense = 12.5 mv 0c to +85c ?1.95 +1.95 % v sense = 75 mv ?40c to +85c ?2.45 +2.45 % v sense = 50 mv ?40c to +85c ?3.85 +3.85 % v sense = 25 mv ?40c to +85c ?6.7 +6.7 % v sense = 12.5 mv ?40c to +85c v sense for adc full scale 105.84 mv this is an absolute value to be used when converting adc codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see specs for current sense absolute accuracy) voltage accuracy ?0.85 +0.85 % v cc = 3 v minimum (low range) 0c to +70c ?0.9 +0.9 % v cc = 6 v minimum (high range) 0c to +70c ?0.85 +0.85 % v cc = 3 v minimum (low range) 0c to +85c ?0.9 +0.9 % v cc = 6 v minimum (high range) 0c to +85c ?0.9 +0.9 % v cc = 3 v minimum (low range) ?40c to +85c ?1.15 +1.15 % v cc = 6 v minimum (high range) ?40c to +85c v cc for adc full scale, low range (vrange = 1) 6.65 v v cc for adc full scale, high range (vrange = 0) 26.35 v these are absolute values to be used when converting adc codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see specs for voltage accuracy) i 2 c timing low level input voltage, v il 0.3 v bus v high level input voltage, v ih 0.7 v bus v low level output voltage on sda, v ol 0.4 v i ol = 3 ma output fall time on sda from v ihmin to v ilmax 20 + 0.1 c b 250 ns c b = bus capacitance from sda to gnd maximum width of spikes suppressed by input filtering on sda and scl pins 50 250 ns input current, i i , on sda/scl when not driving out a logic low ?10 +10 a input capacitance on sda/scl 5 pf scl clock frequency, f scl 400 khz low period of the scl clock 600 ns high period of the scl clock 1300 ns
adm1175 rev. 0 | page 5 of 24 parameter min typ max unit conditions setup time for a repeated start condition, t su;sta 600 ns sda output data hold time, t hd;dat 100 900 ns setup time for a stop condition, t su;sto 600 ns bus free time between a stop and a start condition, t buf 1300 ns capacitive load for each bus line 400 pf 1 monitoring accuracy is a measure of the er ror in a code that is read back for a pa rticular voltage/current. this is a combinat ion of amplifier error, reference error, adc error, and error in adc full-scale code conversion factor.
adm1175 rev. 0 | page 6 of 24 absolute maximum ratings table 2. parameter rating vcc pin 20 v sense pin 20 v timer pin ?0.3 v to +6 v on/onb pin ?0.3 v to +20 v conv pin ?0.3 v to +6 v gate pin 30 v sda pin, scl pin ?0.3 v to +7 v adr pin ?0.3 v to +6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering , 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. thermal resistance package type ja unit 10-lead msop 137.5 c/w esd caution
adm1175 rev. 0 | page 7 of 24 pin configuration and fu nction descriptions vcc 1 sense 2 on/onb 3 gnd 4 timer 5 gate 10 conv 9 adr 8 sda 7 scl 6 adm1175 top view (not to scale) 05647-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vcc positive supply input pin. the operating supply voltage range is from 3.15 v to 16.5 v. an undervoltage lockout (uvlo) circuit resets the adm1175 when a low supply voltage is detected. 2 sense current sense input pin. a sense resistor between th e vcc pin and the sense pin sets the analog current limit. the hot swap operation of the adm1175 controls the external fet gate to maintain the (v vcc ? v sense ) voltage at 100 mv or below. 3 on/onb undervoltage or overvoltage input pin. this pin is active high on the adm1175-1 and adm1175-2 and active-low on the adm1175-3 and adm1175-4. an internal on comparator has a trip threshold of 1.3 v, and the output of this compar ator is used as an enable for the hot swap operation. for the on pin variants with an external resistor divider from vcc to gnd, th is pin can be used to enable the hot swap operation on a specific voltage on vcc, giving an undervoltage function. similarly, for the onb pin variants, an external resistor divider can be used to create an overvoltage function, where the divider sets a voltage on vcc at which the hot swap operation is switched off, pulling the gate to ground. 4 gnd chip ground pin. 5 timer timer pin. an external capacitor, c timer , sets a 270 ms/f initial timing cycle delay and a 21.7 ms/f fault delay. the gate pin turns off when the timer pin is pulled beyond the upper threshold. an overvoltage detection with an external zener can be used to force this pin high. 6 scl i 2 c clock pin. open-drain input requires an external resistive pull-up. 7 sda i 2 c data i/o pin. open-drain input/output. requires an external resistive pull-up. 8 adr i 2 c address pin. this pin can be tied low, tied high, left floating, or tied low through a resistor to set four different i 2 c addresses. 9 conv convert start pin. a high level on this pin enables an adc conversion. the state of an internal control register, which is set through the i 2 c interface, configures the part to convert current only, voltage only, or both channels when the convert pin is asserted. 10 gate gate output pin. this pin is the high-side gate drive of an external n-channel fet. this pin is driven by the fet drive controller, which utilizes a charge pump to provide a 12.5 a pull-up current to charge the fet gate pin. the fet drive controller regulates to a ma ximum load current (100 mv through the sense resistor) by modulating the gate pin.
adm1175 rev. 0 | page 8 of 24 typical performance characteristics 05647-021 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 024681 01 41 12 16 i cc (ma) v cc (v) 8 figure 4. supply current vs. supply voltage 12 10 8 6 4 2 0 01 8 16141210 8642 drive voltage (v) v cc (v) 05647-029 10 12 16 14 8642 i gate (a) v cc (v) figure 5. drive voltage (v gate ? v cc ) vs. supply voltage 0 ?14 ?12 ?10 ?8 ?6 ?4 ?2 01 8 05647-027 figure 6. gate pull-up current vs. supply voltage 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 80 60 40 20 0 ?20 i cc (ma) temperature (c) 05647-022 figure 7. supply current vs. temperature (gate on) 12 10 8 6 4 2 0 ?40 80 60 40 20 0 ?20 drive voltage (v) temperature (c) 5v v cc 3.15v v cc 05647-030 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?40 80 60 40 20 0 ?20 i gate (a) temperature (c) figure 8. drive voltage (v gate ? v cc ) vs. temperature 05647-028 figure 9. gate pull-up current vs. temperature
adm1175 rev. 0 | page 9 of 24 16141210 8642 i gate (ma) v cc (v) 12 10 8 6 4 2 0 01 8 05647-038 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 timer threshold (v) v cc (v) 05647-031 141210 8642 i gate (a) v gate (v) 01 8 10 12 16 14 8642 figure 10. gate pull-down current vs. v cc at v gate = 5 v 2 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 01 6 high low 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 80 high low 60 40 20 0 ?20 timer high threshold (v) temperature (c) 05647-040 20 15 10 5 i gate (ma) v gate (v) figure 11. gate pull-up current vs. gate voltage at v cc = 5 v 0 5 10 15 20 02 5 v cc = 3v v cc = 5v v cc = 12v 05647-043 figure 12. gate pull-down current vs. gate voltage figure 13. timer threshold vs. supply voltage 05647-039 0 100 80 60 40 20 90 70 50 30 10 05 . 0 4.54.03.53.02.5 2.0 1.51.0 0.5 gate on time (ms) c timer (f) 05647-050 figure 14. timer threshold vs. temperature figure 15. current limit on time vs. timer capacitance
adm1175 rev. 0 | page 10 of 24 018 10 12 16 14 8 6 4 2 0 ?1 ?2 ?3 ?4 ?5 ?6 i timer (a) v cc (v) 05647-032 figure 16.timer pull-up current (initial cycle) vs. supply voltage 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 i timer (a) v cc (v) 05647-034 018 10 12 16 14 8 6 4 2 figure 17. timer pull-up current (c. b. delay) vs. supply voltage 3.0 2.5 2.0 1.5 1.0 0.5 0 i timer (a) v cc (v) 05647-036 018 10 12 16 14 8 6 4 2 figure 18. timer pull-down current (cool-off cycle) vs. supply voltage 0 ?1 ?2 ?3 ?4 ?5 ?6 ?40 80 60 40 20 0 ?20 i timer (a) temperature (c) 05647-033 figure 19. timer pull-up current (initial cycle) vs. temperature 0 ?10 ?20 ?30 ?40 ?50 ?80 ?70 ?60 ?40 80 60 40 20 0 ?20 i timer (a) temperature (c) 05647-035 figure 20. timer pull-up current (c. b. delay) vs. temperature 3.0 2.5 2.0 1.5 1.0 0.5 0 ?40 80 60 40 20 0 ?20 i timer (a) temperature (c) 05647-037 figure 21. timer pull-down current (cool-off cycle) vs. temperature
adm1175 rev. 0 | page 11 of 24 120 80 85 90 95 100 105 110 115 218 16 14 12 10 8 6 4 v lim (mv) v cc (v) 05647-041 figure 22. circuit breaker limit voltage vs. supply voltage 110 90 92 94 96 98 100 102 104 106 108 ?40 80 60 40 20 0 ?20 v (mv) temperature (c) v octim v lim v ocfast 05647-042 figure 23. v octim , v lim , v ocfast vs. temperature 05647-026 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 v adr i adr (a) 11 decode 10 decode 01 decode 00 decode figure 24. address pin voltage vs. address pin current for four addressing options 0 1000 900 800 700 600 500 400 300 200 100 hits per code (1000 reads) code 05647-060 2047 2048 2049 2050 2046 figure 25. adc noise, current chan nel, midcode input, 1000 reads 0 1000 900 800 700 600 500 400 300 200 100 hits per code (1000 reads) code 05647-061 780 781 782 783 779 figure 26. adc noise, 14:1 voltage channel, 5 v input, 1000 reads 0 1000 900 800 700 600 500 400 300 200 100 hits per code (1000 reads) code 05647-062 3079 3080 3081 3082 3078 figure 27. adc noise, 7:1 voltage channel, 5 v input, 1000 reads
adm1175 rev. 0 | page 12 of 24 4 3 2 1 0 ?1 ?2 ?3 ?4 0 4000 2500 3000 3500 2000 1500 1000 500 inl (lsb) code 05647-023 figure 28. inl for adc 4 3 2 1 0 ?1 ?2 ?3 ?4 0 4000 2500 3000 3500 2000 1500 1000 500 dnl (lsb) code 05647-024 figure 29. dnl for adc
adm1175 rev. 0 | page 13 of 24 overview of the hot swap function when circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. such transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. the adm1175 is designed to turn a circuit board supply voltage on and off in a controlled manner, allowing the circuit board to be safely inserted into or removed from a live backplane. the adm1175 can reside either on the backplane or on the circuit board itself. the adm1175 controls the inrush current to a fixed maximum level by modulating the gate of an external n-channel fet placed between the live supply rail and the load. this hot swap function protects the card connectors and the fet itself from damage and limits any problems that can be caused by high current loads on the live supply rail. the adm1175 holds the gate pin down (and, thus, the fet is held off) until a number of conditions are met. an undervoltage lockout circuit ensures that the device is provided with an adequate input supply voltage. once the input supply voltage has been successfully detected, the device goes through an initial timing cycle to provide a delay before it attempts to hot swap. this delay ensures that the board is fully seated in the backplane before the board is powered up. once the initial timing cycle is complete, the hot swap function is switched on under control of the on/onb pin. when on/onb is asserted (high for the adm1175-1 and adm1175-2, low for the adm1175-3 and adm1175-4), the hot swap operation starts. the adm1175 charges up the gate of the fet to turn on the load. it continues to charge up the gate pin until the linear current limit (set to 100 mv/r sense ) is reached. for some combi- nations of low load capacitance and high current limit, this limit may not be reached before the load is fully charged up. if current limit is reached, the adm1175 regulates the gate pin to keep the current at this limit. for currents above the overcurrent fault timing threshold, nominally 100 mv/r sense , the current fault is timed by sourcing a current out to the timer pin. if the load becomes fully charged before the fault current limit time is reached (when the timer pin reaches 1.3 v), the current drops below the overcurrent fault timing threshold. the adm1175 then charges the gate pin higher to fully enhance the fet for lowest r on , and the timer pin is pulled down again. if the fault current limit time is reached before the load drops below the current limit, a fault has been detected, and the hot swap operation is aborted by pulling down on the gate pin to turn off the fet. the adm1175-2 and adm1175-4 are latched off. they attempt to hot swap again only when the on/onb pin is deasserted and then asserted again. the adm1175-1 and adm1175-3 retry the hot swap operation indefinitely, keeping the fet in its safe operating area (soa) by using the timer pin to time a cool-down period in between hot swap attempts. the current and voltage threshold combinations on the timer pin set the retry duty cycle to 3.8%. the adm1175 is designed to operate over a range of supplies from 3.15 v to 16.5 v. undervoltage lockout an internal undervoltage lockout (uvlo) circuit resets the adm1175 if the vcc supply is too low for normal operation. the uvlo has a low-to-high threshold of 2.8 v, with 80 mv hysteresis. above 2.8 v supply voltage, the adm1175 starts the initial timing cycle. on/onb function the adm1175-1 and adm1175-2 have an active high on pin. the on pin is the input to a comparator that has a low-to-high threshold of 1.3 v, a 50 mv hysteresis, and a glitch filter of 3 s. a low input on the on pin turns off the hot swap operation by pulling the gate pin to ground, turning off the external fet. the timer pin is also reset by turning on a pull-down current on this pin. a low-to-high transition on the on pin starts the hot swap operation. a 10 k pull-up resistor connecting the on pin to the supply is recommended. alternatively, an external resistor divider at the on pin can be used to program an undervoltage lockout value higher than the internal uvlo circuit, thereby setting a voltage level at the vcc supply, where the hot swap operation is to start. an rc filter can be added at the on pin to increase the delay time at card insertion if the initial timing cycle delay is insufficient. the adm1175-3 and adm1175-4 have an active low onb pin. this pin operates exactly as described above for the on pin, but the polarity is reversed. this allows this pin to function as an overvoltage detector that can use the external fet as a circuit breaker for overvoltage conditions on the monitored supply. timer function the timer pin handles several timing functions with an external capacitor, c timer . there are two comparator thresholds: v timerh (0.2 v) and v timerl (1.3 v). the four timing current sources are a 5 a pull-up, a 60 a pull-up, a 2 a pull-down, and a 100 a pull-down. the 100 a pull-down is a non-ideal current source, approximating a 7 k resistor below 0.4 v. these current and voltage levels, together with the value of c timer chosen by the user, determine the initial timing cycle time, the fault current limit time, and the hot swap retry duty cycle.
adm1175 rev. 0 | page 14 of 24 gate and timer functions during a hot swap during hot insertion of a board onto a live supply rail at vcc, the abrupt application of supply voltage charges the external fet drain/gate capacitance, which can cause an unwanted gate voltage spike. an internal circuit holds gate low before the internal circuitry wakes up. this reduces the fet current surges substan- tially at insertion. the gate pin is also held low during the initial timing cycle and until the on pin has been taken high to start the hot swap operation. during hot swap operation, the gate pin is first pulled up by a 12 a current source. if the current through the sense resistor reaches the overcurrent fault timing threshold, v octim , a pull-up current of 60 a on the timer pin, is turned on, and this pin starts charging up. at a slightly higher voltage in the sense resistor, the error amplifier servos the gate pin to maintain a constant current to the load by controlling the voltage across the sense resistor to the linear current limit, v lim . a normal hot swap is complete when the board supply capaci- tors near full charge, and the current through the sense resistor drops to eventually reach the level of the board load current. as soon as the current drops below the overcurrent fault timing threshold, the current into the timer pin switches from being a 60 a pull-up to a 100 a pull-down. the adm1175 then drives the gate voltage as high as it can to fully enhance the fet and reduce r on losses to a minimum. a hot swap fails if the load current does not drop below the overcurrent fault timing threshold, v octim , before the timer pin has charged up to 1.3 v. in this case, the gate pin is then pulled down with a 2 ma current sink. the gate pull-down stays on until a hot swap retry starts, which can be forced by deasserting and then reasserting the on/onb pin. on the adm1175-1 and adm1175-3, the device retries automatically after a cool-down period. the adm1175 also features a method of protection from sudden load current surges, such as a low impedance fault, when the current seen across the sense resistor may go well beyond the linear current limit. if the fast overcurrent trip threshold, v ocfast , is exceeded, the 2 ma gate pull-down is turned on immediately. this pulls the gate voltage down quickly to enable the adm1175 to limit the length of the current spike that gets through, and also to bring the current through the sense resistor back into linear regulation as quickly as possible. this process protects the backplane supply from sustained overcurrent conditions that can otherwise cause the backplane supply to droop during the overcurrent event. calculating current limits and fault current limit time the nominal linear current limit is determined by a sense resistor connected between the vcc pin and the sense pin, as given by equation 1. i limit(nom) = v lim(nom) /r sense = 100 mv/ r sense (1) the minimum linear fault current is given by equation 2. i limit(min) = v lim(min) /r sense(max) = 90 mv/ r sense(max) (2) the maximum linear fault current is given by equation 3. i limit(max) = v lim(max) /r sense(min) = 110 mv/ r sense(min) (3) the power rating of the sense resistor should be rated at the maximum linear fault current level. the minimum overcurrent fault timing threshold current is given by equation 4. i octim(min) = v octim(min) /r sense(max) = 85 mv/ r sense(max) (4) the maximum fast overcurrent trip threshold current is given by equation 5. i ocfast(max) = v ocfast(max) / r sense(min) = 115 mv/ r sense(min) (5) the fault current limit time is the time that a device spends timing an overcurrent fault, and is given by equation 6. t fault 21.7 c timer ms/f (6) initial timing cycle when vcc is first connected to the backplane supply, the internal supply (time point (1) in figure 30 ) of the adm1175 must be charged up. a very short time later (significantly less than 1 ms), the internal supply is fully up and, because the undervoltage lockout voltage has been exceeded at vcc, the device comes out of reset. during this first short reset period, the gate pin is held down with a 25 ma pull-down current, and the timer pin is pulled down with a 100 a current sink. the adm1175 then goes through an initial timing cycle. at time point (2), the timer pin is pulled high with 5 a. at time point (3), the timer reaches the v timerl threshold, and the first portion of the initial cycle ends. the 100 a current source then pulls down the timer pin until it reaches 0.2 v at time point (4). the initial cycle delay (time point (2) to time point (4)) is related to c timer by equation 7. t initial 270 c timer ms/f (7)
adm1175 rev. 0 | page 15 of 24 when the initial timing cycle terminates, the device is ready to start a hot swap operation (assuming the on/onb pin is asserted). in the example shown in figure 30 , the on pin is asserted at the same time that v cc is applied, so the hot swap operation starts immediately after time point (4). at this point, the fet gate is charged up with a 12 a current source. at time point (5), the threshold voltage of the fet is reached, and the load current begins to flow. the fet is controlled to keep the sense voltage at 100 mv (this corresponds to a maximum load current level defined by the value of r sense ). at time point (6), v gate and v out have reached their full potential, and the load current has settled to its nominal level. figure 31 illustrates the situation where the on pin is asserted after v cc is applied. v vcc (1) initial timing cycle (2) (3) (4) (5) (6) v on v timer v gate v sense v out 05647-004 figure 30. startup (on asse rts as power is applied) initial timing cycle v vcc v on v timer v gate v sense v out (1) (2) (3) (4) (5)(6) (7) 05647-005 figure 31. startup (on asserts after power is applied) hot swap retry cycle on the adm1175-1 and the adm1175-3 with the adm1175-1 and the adm1175-3, the device turns off the fet after an overcurrent fault and then uses the timer pin to time a delay before automatically retrying to hot swap. as with all adm1175 devices, on overcurrent fault is timed by charging the timer cap with a 60 a pull-up current. when the timer pin reaches 1.3 v, the fault current limit time has been reached, and the gate pin is pulled down. on the adm1175-1 and the adm1175-3, the timer pin is then pulled down with a 2 a current sink. when the timer pin reaches 0.2 v, it automatically restarts the hot swap operation. the cool-down period is related to c timer by equation 8. t cool 550 c timer ms/f (8) thus, the retry duty cycle is given by equation 9. t fault /(t cool + t fault ) 100% = 3.8% (9)
adm1175 rev. 0 | page 16 of 24 voltage and current readback in addition to providing hot swap functionality, the adm1175 also contains the components to allow voltage and current readback over an inter-ic (i 2 c) bus. the voltage output of the current sense amplifier and the voltage on the vcc pin are fed into a 12-bit adc via a multiplexer. the device can be instructed to convert voltage and/or current at any time during operation via an i 2 c command or an assertion on the convert start (conv) pin. when all conversions are complete, the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. serial bus interface control of the adm1175 is carried out via the i 2 c bus. this interface is compatible with i 2 c fast mode (400 khz maximum). the adm1175 is connected to this bus as a slave device, under the control of a master device. identifying the adm1175 on the i 2 c bus the adm1175 has a 7-bit serial bus slave address. when the device powers up, it does so with a default serial bus address. the five msbs of the address are set to 11010; the two lsbs are deter- mined by the state of the adr pin. there are four different configurations available on the adr pin that correspond to four different i 2 c addresses for the two lsbs (see table 5). this scheme allows four adm1175 devices to operate on a single i 2 c bus. table 5. setting i 2 c addresses via the adr pin adr configuration address low state 0xd0 resistor to gnd 0xd2 floating (unconnected) 0xd4 high state 0xd6 general i 2 c timing figure 32 and figure 33 show timing diagrams for general read and write operations using the i 2 c. the i 2 c specification defines conditions for different types of read and write operations, which are discussed later. the general i 2 c protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, sda, while the serial clock line scl remains high. this indicates that a data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (msb first), plus an r/ w bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus remain idle, while the selected device waits for data to be read from it or written to it. if the r/ w bit is 0, the master writes to the slave device. if the r/ w bit is 1, the master reads from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to- high transition when the clock is high can be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it can be an instruction, such as telling the slave device to expect a block write; or it can be a register address that tells the slave where subse- quent data is to be written. because data can flow in only one direction, as defined by the r/ w bit, it is not possible to send a command to a slave device during a read operation. before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low. this is known as a no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.
adm1175 rev. 0 | page 17 of 24 scl sda start by master 1 9 1 9 a1 a0 r/w 1 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 acknowledge by slave acknowledge by slave acknowledge by slave acknowledge by slave frame 1 slave address frame 2 command code scl (continued) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 stop by master sda (continued) frame 3 data byte frame n data byte 05647-006 figure 32. general i 2 c write timing diagram scl sda start by master 1 9 1 9 a1 a0 r/w 1 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 acknowledge by slave acknowledge by master no acknowledge acknowledge by master frame 1 slave address frame 2 data byte scl (continued) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 stop by master sda (continued) frame 3 data byte frame n data byte 05647-007 figure 33. general i 2 c read timing diagram sclscl sda p s t hd;sta t hd;dat t high t su;dat t su;sta t hd;sta t f t r t low t buf t su;sto p s 05647-008 figure 34. serial bus timing diagram
adm1175 rev. 0 | page 18 of 24 write and read operations the i 2 c specification defines several protocols for different types of read and write operations. the operations used in the adm1175 are discussed in the sections that follow. table 6 shows the abbreviations used in the command diagrams. table 6. i 2 c abbreviations abbreviation condition s start p stop r read w write a acknowledge n no acknowledge quick command the quick command operation allows the master to check if the slave is present on the bus, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. s slave address wa 12 3 05647-009 figure 35. quick command write command byte in the write command byte operation the master device sends a command byte to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends the command byte. the command byte is identified by an msb = 0. an msb = 1 indicates an extended register write (see the write extended byte section). 5. the slave asserts an acknowledge on sda. 6. the master asserts a stop condition on sda to end the transaction. s slave address wa command byte ap 12 3 456 05647-010 figure 36. write command byte the seven lsbs of the command byte are used to configure and control the adm1175. table 7 provides details of the function of each bit. table 7. command byte operations bit default name function c0 0 v_cont set to convert voltage continuously. if readback is attempted before the first conversion is complete, the adm1175 asserts an acknowledge and returns all 0s in the returned data. c1 0 v_once set to convert voltage once. self-clears. i 2 c asserts a no acknowledge on attempted reads until the adc conversion is complete. c2 0 i_cont set to convert voltage continuously. if readback is attempted before the first conversion is complete, the adm1175 asserts an acknowledge and returns all 0s in the returned data. c3 0 i_once set to convert current once. self-clears. i 2 c asserts a no acknowledge on attempted reads until adc conversion is complete. c4 0 vrange selects different internal attenuation resistor networks for voltage readback. a 0 in c4 selects a 14:1 voltage divider. a 1 in c4 selects a 7:2 voltage divider. with an adc full scale of 1.902 v, the voltage at the vcc pin for an adc full-scale result is 26.35 v for vrange = 0 and 6.65 v for vrange = 1. c5 0 n/a unused. c6 0 status_rd status read. when this bit is set, the data byte read back from the adm1175 is the status byte. it contains the status of the device alerts. see table 15 for full details of the status byte.
adm1175 rev. 0 | page 19 of 24 write extended byte in the write extended byte operation, the master device writes to one of the three extended registers of the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends the register address byte. the msb of this byte is set to 1 to indicate an extended register write. the two lsbs indicate which of the three extended registers are to be written to (see table 8 ). all other bits should be set to 0. 5. the slave asserts an acknowledge on sda. 6. the master sends the command byte. the command byte is identified by an msb = 0. an msb = 1 indicates an extended register write. 7. the slave asserts an acknowledge on sda. 8. the master asserts a stop condition on sda to end the transaction. s slave address wa register address ap register data a 12 34 56 78 05647-011 figure 37. write extended byte table 9 , table 1 0 , and table 11 give details of each extended register. table 8. extended register addresses a6 a5 a4 a3 a2 a1 a0 extended register 0 0 0 0 0 0 1 alert_en 0 0 0 0 0 1 0 alert_th 0 0 0 0 0 1 1 control table 9. alert_en register operations bit default name function 0 0 en_adc_oc1 enabled if a single adc conversion on the i chan nel has exceeded the threshold set in the alert_th register. 1 0 en_adc_oc4 enabled if four consecutive adc conversions on the i channel have exceeded the threshold set in the alert_th register. 2 1 en_hs_alert enabled if the hot swap has either latched off or entered a cool-down cycle because of an overcurrent event. 3 0 en_off_alert enables an alert if the hs operation is turned off by a transition that deasserts the on/onb pin or by an operation that writes the swoff bit high. 4 0 clear clears the on_alert, hs_alert and adc_alert sta tus bits in the status register. these can immediately reset if the source of the alert has not been cleared or disabled with the other bits in this register. this bit self-clears to 0 after the status register bits have been cleared. table 10. alert_th register operations bit default function 7:0 ff the alert_th register sets the current level at which an al ert occurs. defaults to adc full scale. the alert_th 8-bit number corresponds to the top eight bits of the current channel data. table 11. control register operations bit default name function 0 0 swoff forces hot swap off. equivalent to deasserting the on/onb pin.
adm1175 rev. 0 | page 20 of 24 read voltage and/or current data bytes the adm1175 can be set up to provide information in three different ways (see the write command byte section). depending on how the device is configured, the following data can be read out of the device after a conversion (or conversions). voltage and current readback the adm1175 digitizes both voltage and current. three bytes are read out of the device in the format shown in table 12 . table 12. voltage and current readback format byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 voltage msbs v11 v10 v9 v8 v7 v6 v5 v4 2 current msbs i11 i10 i9 i8 i7 i6 i5 i4 3 lsbs v3 v2 v1 v0 i3 i2 i1 i0 voltage readback the adm1175 digitizes voltage only. two bytes are read out of the device in the format shown in table 13 . table 13. voltage only readback format byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 voltage msbs v11 v10 v9 v8 v7 v6 v5 v4 2 voltage lsbs v3 v2 v1 v0 0 0 0 0 current readback the adm1175 digitizes current only. two bytes are read out of the device in the format shown in table 14 . table 14. current only readback format byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 current msbs i11 i10 i9 i8 i7 i6 i5 i4 2 current lsbs i3 i2 i1 i0 0 0 0 0 the following series of events occurs when the master receives three bytes (voltage and current data) from the slave device: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. the master receives the first data byte. 5. the master asserts acknowledge on sda. 6. the master receives the second data byte. 7. the master asserts an acknowledge on sda. 8. the master receives the third data byte. 9. the master asserts a no acknowledge on sda. 10. the master asserts a stop condition on sda, and the transaction ends. for cases where the master is reading voltage only or current only, only two data bytes are read. step 7 and step 8 are not required. s slave address ra data 1 data 2 np data 3 a a 12 345678910 05647-012 figure 38. three-byte read from adm1175 s slave address ra register address np register data a 12 34 56 78 05647-013 figure 39. two-byte read from adm1175 converting adc codes to voltage and current readings the following equations can be used to convert adc codes representing voltage and current from the adm1175 12-bit adc into actual voltage and current values. voltage = ( v fullscale /4096) code where: v fullscale = 6.65 (7:2 range) or 26.35 (14:1 range). code is the adc voltage code read from the device (bit v0 to v11). current = (( i fullscale /4096) code)/ sense resistor where: i fullscale = 105.84 mv. code is the adc current code read from the device (bit i0 to bit i11). read status register a single register of status data can also be read from the adm1175. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. the master receives the status byte. 5. the master asserts an acknowledge on sda. s slave address ra data 1 a 12 345 05647-014 figure 40. status read from adm1175 table 15 shows the adm1175 status registers in detail. note that bit 1, bit 3, and bit 5 are cleared by writing to bit 4 of the alert_en register (clear).
adm1175 rev. 0 | page 21 of 24 table 15. status byte operations bit name function 0 adc_oc an adc-based overcurrent comparison has been detected on the last three conversions 1 adc_alert an adc-based overcurrent trip has happened, which has caused the alert. cleared by writing to bit 4 of the alert_en register. 2 hs_oc the hot swap is off due to an analog over current event. on parts that latch off, this is the same as the hs_alert status bit (if en_hs_alert = 1). on the retry parts, this indicates the current state: a 0 can indicate that the data was read during a period when the device was retrying, or that it has successfully hot swapped by retrying after at least one overcurrent timeout. 3 hs_alert the hot swap has failed since th e last time this was reset. cleared by writing to bit 4 of the alert_en register. 4 off_status the state of the on/onb pin. set to 1 if the input pin is dea sserted. can also be set to 1 by writing to the swoff bit of the control register. 5 off_alert an alert has been caused by either the on/onb pin or th e swoff bit. cleared by writing to bit 4 of the alert_en register.
adm1175 rev. 0 | page 22 of 24 applications waveforms 05647-070 ch1 1.5a ch2 1.00v ch3 20.0v ch4 10.0v m40.0ms 4 3 2 1 figure 41. inrush current control into 220 f load (ch1 = i load , ch2 = v timer , ch3 = v gate , ch4 = v out ) 05647-071 ch1 1.5a ch2 1.00v ch3 20.0v ch4 10.0v m10.0ms 4 3 2 1 figure 42. overcurrent condition at startup (adm1175-1 model) (ch1 = i load , ch2 = v timer , ch3 = v gate , ch4 = v out ) 05647-072 ch1 1.5a ch2 1.00v ch3 20.0v ch4 10.0v m20.0ms 4 3 2 1 figure 43. overcurrent condition at startup (adm1175-2 model) (ch1 = i load , ch2 = v timer , ch3 = v gate , ch4 = v out ) 05647-073 ch1 1.5a ch2 1.00v ch3 20.0v ch4 10.0v m10.0ms 4 3 2 1 figure 44. overcurrent condition du ring operation (adm1175-1 model) (ch1 = i load , ch2 = v timer , ch3 = v gate , ch4 = v out ) 05647-074 ch1 1.5a ch2 1.00v ch3 20.0v ch4 10.0v m20.0ms 4 3 2 1 figure 45. overcurrent condition du ring operation (adm1175-2 model) (ch1 = i load , ch2 = v timer , ch3 = v gate , ch4 = v out )
adm1175 rev. 0 | page 23 of 24 kelvin sense resistor connection when using a low value sense resistor for high current measurement, the problem of parasitic series resistance may arise. the lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. this problem can be avoided by using a kelvin sense connection. this type of connection separates the current path through the resistor and the voltage drop across the resistor. figure 46 shows the correct way to connect the sense resistor between the vcc pin and the sense pin of the adm1175. sense resistor kelvin sense traces vcc sense adm1175 current flow from supply current flow to load 05647-015 figure 46. kelvin sense connections
adm1175 rev. 0 | page 24 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 47. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model hot swap retry option on/onb pin temperature range package description package option branding adm1175-1armz-r7 1 automatic retry version on ?40c to +85c 10-lead msop rm-10 m5p ADM1175-2ARMZ-R7 1 latched off version on ?40c to +85c 10-lead msop rm-10 m5r adm1175-3armz-r7 1 automatic retry version onb ?40c to +85c 10-lead msop rm-10 m5s adm1175-4armz-r7 1 latched off version onb ?40c to +85c 10-lead msop rm-10 m5t eval-adm1175ebz 1 evaluation board 1 z = pb-free part. purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05647-0-9/06(0)

▲Up To Search▲

Price & Availability of ADM1175-2ARMZ-R7

	To Download ADM1175-2ARMZ-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .